Lehre.DigDesLab (Struktur)

Design Lab of Digital Systems

(G. Kemnitz, C. Giesemann)

It is a block course for English speaking IASTE and ITIS students taking place in May and June. The course starts with lab exercises in digital circuit design using VHDL: simulation, synthesis, programming into Xilinx-FPGAs and test. ...
The difficuilty of the lessons increases from combinatorial circuits of a few gates up to simple graphic adapter functions. In the second part of the course processor systems will be assembled out of predesigned soft cores: processors, memory controllers etc. Programming language will be C. Finally every participant will choose and perform an individual project.

Block 1: Introduction to VHDL

LectureTopicHandout SheetData Sheets an Pices of programms
[A1] Design, Simulation and Test of a Combinational Circuit [H1] [PrVHDL-A1.zip]
[A2] Linear Feedback Shift Registers and Logic Analysis [H2] [PrVHDL-A2.zip]
[A3] Asynchronous Input Signals [H3]
[A4] Seven Segment Display [H4]
[A5] Combination Lock [H5]
Traffic Light Control

Block 2: Softprocessor

LectureTopicHandout SheetData Sheets and Pieces of programs
[SP1] Introduction
[SP2] Basic Course C-Programming
[SP3] Datatypes, functions and header
[SP4] Arrays, Pointer and Bit-manipulation

Autor: gkemnitz, Letzte Änderung: 15.05.2024 10:13:29

 TU Clausthal 2020  Impressum