kamera Project Status (03/04/2010 - 12:26:15)
Project File: kamera.ise Implementation State: Programming File Generated
Module Name: Kamera
  • Errors:
No Errors
Target Device: xc3s1000-5ft256
  • Warnings:
710 Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
X 3 Failing Constraints
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
105657 (Setup: 105657, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
kamera Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 555 15,360 3%  
Number of 4 input LUTs 810 15,360 5%  
Number of occupied Slices 588 7,680 7%  
    Number of Slices containing only related logic 588 588 100%  
    Number of Slices containing unrelated logic 0 588 0%  
Total Number of 4 input LUTs 981 15,360 6%  
    Number used as logic 810      
    Number used as a route-thru 171      
Number of bonded IOBs 161 173 93%  
    IOB Flip Flops 157      
Number of MULT18X18s 1 24 4%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 1 4 25%  
Average Fanout of Non-Clock Nets 3.06      
 
Performance Summary [-]
Final Timing Score: 105657 (Setup: 105657, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 3 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 4. Mrz 12:21:38 20100110 Warnings18 Infos
Translation ReportCurrentDo 4. Mrz 12:22:13 2010000
Map ReportCurrentDo 4. Mrz 12:22:58 20100570 Warnings3 Infos
Place and Route ReportCurrentDo 4. Mrz 12:25:42 2010017 Warnings3 Infos
Post-PAR Static Timing ReportCurrentDo 4. Mrz 12:25:53 2010003 Infos
Bitgen ReportCurrentDo 4. Mrz 12:26:12 2010013 Warnings1 Info
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 03/04/2010 - 12:26:15