library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TP is Port ( CLK: in std_logic; Counts: in NATURAL; Input: in std_logic; Takt: out std_logic; Output: out std_logic ); end TP; architecture Behavioral of TP is begin process(CLK) variable positiv: NATURAL := 0; variable negativ: NATURAL := 0; variable Takt_helper : std_logic := '0'; begin if (CLK'event and (CLK='1')) then if Input = '1' then positiv := positiv + 1; else negativ := negativ + 1; end if; if (positiv+negativ) >= Counts then if positiv > negativ then Output <= '1'; else Output <= '0'; end if; positiv := 0; negativ := 0; Takt_helper := not Takt_helper; Takt <= Takt_helper; end if; end if; end process; end Behavioral;