Lehre.DigDesLab (Struktur)


Design Lab of Digital Systems

(G. Kemnitz, C. Giesemann)

It is a block course for English speaking IASTE and ITIS students taking place in May and June. The course starts with lab exercises in digital circuit design using VHDL: simulation, synthesis, programming into Xilinx-FPGAs and test. ...
The difficuilty of the lessons increases from combinatorial circuits of a few gates up to simple graphic adapter functions. In the second part of the course processor systems will be assembled out of predesigned soft cores: processors, memory controllers etc. Programming language will be C. Finally every participant will choose and perform an individual project.

Block 1: Introduction to VHDL

ExerciseTopicHandout SheetData Sheets an Pieces of programs
[A1] Design, Simulation and Test of a Combinational Circuit [H1] [PrVHDL-A1.zip]
[A2] Linear Feedback Shift Registers and Logic Analysis [H2] [PrVHDL-A2.zip]
[A3] Asynchronous Input Signals [H3]
[A4] Seven Segment Display [H4]
[A5] Combination Lock [H5]

Block 2: Complex Circuits in VHDL

ExerciseTopicData Sheets and Pieces of programs
[B1] Traffic Light Control
[B2] PS/2 Keyboard [a2_ps2.ucf] [a2_ps2.vhd] [a2_ps2.xise] [a2_ps2.xml]
[B3] Serial Interface (RS232) [a3_rs232.ucf] [a3_rs232.vhd] [a3_rs232.xise] [a3_rs232.xml] [a3_rs232_tb.vhd]
[B4] Thermometer + heating and cooling controller [a4_pwm.ucf] [a4_pwm.vhd] [a4_pwm.xise]
[B5] VGA controller [a5_vga.ucf] [a5_vga.vhd] [a5_vga.xise]
[B6] Plotter

Block 3: Softprocessor

ExerciseTopicHandout SheetData Sheets and Pieces of programs
[SP1] Introduction
[SP2] Basic Course C-Programming
[SP3] Datatypes, functions and header
[SP4] Arrays, Pointer and Bit-manipulation

Slides of the corresponding lecture

In the following slides only parts are translated to english: [1] [2] [4]


Autor: gkemnitz, Letzte Änderung: 05.04.2013 13:21:20


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